1. Field of the Invention
The invention relates to a semiconductor device which is provided with a MIS (Metal Insulator Semiconductor) type of FET (Field Effect Transistor) in a trench-isolated region and a method of manufacturing the same.
2. Description of the Related Art
In recent years, to increase the packing density of semiconductor integrated circuits, the conventional LOCOS (Local Oxidation of Silicon) isolation has been replaced with the trench isolation which provides a high electrical isolation capability with insulating layers of narrower width. With the usual trench isolation structure, a single device isolation insulating layer is merely embedded in given locations in a semiconductor substrate. The use of this trench isolation structure for formation of a MISFET will result in such problems as described below.
Reference will be made to FIGS. 1A, 1B and 1C to describe the problems with a conventional flat type of MISFET using the trench isolation. FIG. 1A is a plan view of a MISFET, and FIGS. 1B and 1C are sectional views of the MISFET taken along the line 1B--1B and the line 1C-1C, respectively, of FIG. 1A. In these figures, reference numeral 1 denotes a semiconductor substrate, 3 a buried device isolation insulating layer, 8 a gate electrode, 9 a source/drain region, and 12 a gate insulating layer.
Conventionally, the gate insulating layer 12 is formed after the formation of the device isolation insulating layer 3 and the gate electrode 8 is subsequently formed over the gate insulating layer. In order to expose the surface of the semiconductor substrate 1 after the device isolation insulating layer 3 has been embedded, it is required to etch back the insulating layer. In this case, the insulating layer 3 is apt to be overetched, which will result in the surface of the insulating layer becoming lower than the exposed surface of the semiconductor substrate 1 as shown in FIG. 1B. Consequently, in a portion indicated at b, the edge of the semiconductor substrate 1 is exposed. A gate electric field will concentrate in this exposed portion when a transistor is formed and operated. Thus, the threshold voltage in the portion b becomes lower than in the flat portion a, resulting in a parasitic transistor being formed.
The ratio in conductance of the parasitic transistor to the transistor in the flat portion becomes large as the gate width decreases and each of these transistors will have a different threshold voltage. For this reason, with an integrated circuit in which there are formed a large number of transistors which are different in gate width, the generation of parasitic transistors will result in serious problems in circuit design.
In general, the shape of the semiconductor region and the device isolation region varies in the neighborhood of the parasitic transistor, depending on the amount of etching involved in preprocessing for the formation of the gate insulating layer and the trench shape. For this reason, the electrical characteristics of transistors vary, deteriorating the reproducibility of transistor characteristics.
As described above, the problem with the conventional trench isolation structure in which the device isolation insulating layer is made of a single layer is that parasitic transistors having their threshold voltages lowered are formed because preprocessing for the formation of the gate insulating layer in MISFETs overetches the device isolation insulating layer with the result that the insulating layer becomes lower than the semiconductor region and the edges of the semiconductor region are exposed.